A methodology for simulation of hybrid Single-electron/MOS transistor circuits (Superficies y Vacío, 2013)
On one side, the steady downscaling that CMOS technology has experienced in the last four decades has brought it near its fundamental limits due to the appearance of quantum effects which were not previously taken into account. On the other side, — and even though the current problems involved in their fabrication, nanoelectronic devices such as the Single- Electron Transistors (SET) are devised as future basic cell in the development of electronic systems. It clearly results that in forthcoming years, mature nanometric CMOS devices will share scenario with single-electron devices and other nano-devices in a wide number of applications, yielding hybrid electronic systems. Therefore, it becomes imperative to develop design verifi cation methods and tools specially suited for these hybrid systems. In this paper, we present a simulation methodology for the electrical simulation of hybrid SET/MOS IC designs. The methodology results in a piecewise linear representation of the static SET characteristic that can be easily combined with existing MOS models in a standard industry package for electrical simulation such a SPICE.